On the Design of a Function Specific Reconfigurable Hardwre Accelerator for the MAC-Layer in WLANs

Faculty/Professorship: Information Systems and Energy Efficient Systems  
Author(s): Pionteck, Thilo; Staake, Thorsten ; Stiefmeier, Thomas; Kabulepa, Lukusa D.; Glesner, Manfred
Title of the compilation: Proceedings of the 2004 ACMSIGDA 12th international symposium on Field programmable gate arrays
Corporate Body: FPGA '04: 2004 ACM\/SIGDA 12th international symposium on Field programmable gate arrays
Publisher Information: New York, NY, USA : ACM
Year of publication: 2004
Pages: 258
ISBN: 1-58113-829-6
Language(s): English
DOI: 10.1145/968280.968352
URL: http://dl.acm.org/citation.cfm?id=968352
This work presents the hardware design of a dynamically reconfigurable function unit (RFU) to accelerate computation-intensive tasks in Medium Access Control (MAC) layers of WLANs. The function unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for the Advanced Encryption Standard (AES) as specified in upcoming WLAN standards such as IEEE 802.11i. Dynamic reconfiguration allows the processor to use arithmetic components and memory elements of the RFU not only for AES, but also for additional tasks common in the MAC-layer. With our approach it is possible to accelerate Reed-Solomon-Code generation, Cyclic Redundancy Checks as well as other encryption standards like SQUARE, Magenta and Twofish by supporting Galois Field multiplication and table look-ups. The integration of the reconfigurable unit in the processor core results in an architecture that can simultaneously support control-flow and data-flow oriented tasks. This architecture was prototyped onto a Virtex2 FPGA.
Type: Conferenceobject
URI: https://fis.uni-bamberg.de/handle/uniba/3188
Year of publication: 22. April 2014