Pionteck, ThiloThiloPionteckStiefmeier, ThomasThomasStiefmeierStaake, ThorstenThorstenStaakeGlesner, ManfredManfredGlesner2019-09-192014-04-2220071868-4238https://fis.uni-bamberg.de/handle/uniba/3193This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed- Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.engarticle10.1007/978-0-387-73661-7_18http://link.springer.com/chapter/10.1007%2F978-0-387-73661-7_18